The present technology relates to a three-dimensional (3D) shape generation method, a program for causing a computer to execute the 3D shape generation method, and a recording medium recording the program.
When semiconductor apparatuses are designed, process simulations or device simulations are used for the purpose of saving design time or reducing prototyping or manufacturing costs.
In the process simulations, the shape of a surface or interface and the movement or deterioration of a material included in a semiconductor apparatus associated with a manufacturing process are reproduced on a computer according to a specified physical law.
In the device simulations, characteristics of electronic elements are reproduced on a computer by adding electrical operation conditions for a shape or material distribution determined by the process simulations.
In the process simulations, a series of process steps of manufacturing the semiconductor apparatus are reproduced on the computer. The process steps include deposition (adding a material to a surface), etching (removing a material from a surface), lithography (specifying a surface processing region), and other processes.
The process simulations are roughly classified into shape (topography) simulation and bulk process simulation.
The topography simulation is used for simulations of process steps such as deposition, etching, and lithography, and related to a change in a shape of a material including a semiconductor wafer.
The bulk process simulation can be used for simulations of process steps mainly related to redistributions of dopant impurities among semiconductor elements such as diffusion, ion implantation, oxidation, and the like.
One of the purposes of the process simulations is to create a computer representation of a microscopic structure formed on a wafer surface and use the computer representation in bulk process simulation, device simulation, and other analysis programs.
According to the device simulations or other analysis programs, characteristics such as electrical characteristics, temperature characteristics, and mechanical characteristics of a semiconductor apparatus can be calculated.
An operation of an element constituting the semiconductor apparatus is specified by a shape and composition distribution of a microscopic structure formed on a wafer surface.
Technology for accurately performing a predictive calculation of a shape of the microscopic structure obtained as the result of the processes of etching, deposition, and lithography has been developed so far.
In addition, a method of representing a shape of a surface or interface on a computer is also shown in several types.
Representative shape-describing methods adopted for the shape simulation, for example, are a cell model (for example, see Japanese Patent Application Publication No. 2007-123485), a network model, a diffusion model, and a string model (for example, see Japanese Patent Application Publication No. 2000-160336).
In the device simulations or other analysis programs, a set (analysis mesh) of coordinate points on which numerical analysis is performed is generated from a shape-describing format. Because the analysis mesh specifies the precision of physical simulations of an operation of an element, it is necessary to reproduce an actual shape of an element on the computer with high precision, that is, it is necessary to precisely represent a 3D curved surface of a boundary and surface between materials.
However, the cell model, the network model, the diffusion model, and the string model described above all have a limitation in precisely representing a 3D curved surface of a boundary and surface between materials.
In terms of problems of the above-described models, attempts to initially specify a shape-describing format suitable for highly precise analysis in an analysis program and then construct a simulation method for the specified shape-describing format have been reported (for example, see Japanese Patent Application Publication No. H6-28429).
In Japanese Patent Application Publication No. H6-28429, a method of extending a well-known solid modeling function and performing process simulations in manufacturing of a semiconductor apparatus is disclosed.
In addition, several methods of describing a shape using solid modeling have been proposed (for example, see Japanese Patent Application Publication Nos. 2004-327810, H10-41366, and 2008-244293).
The solid modeling traditionally means a 3D shape generation method and program adopted for a computer-aided design (CAD) tool, and enables an inherently substantially static physical structure such as a building to be easily designed or assembled.